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MX29F001T/B
1M-BIT [128K x 8] CMOS FLASH MEMORY FEATURES
5.0V 10% for read, erase and write operation 131072x8 only organization Fast access time: 55/70/90/120ns Low power consumption - 30mA maximum active current(5MHz) - 1uA typical standby current * Command register architecture - Byte Programming (7us typical) - Sector Erase (8K-Byte x 1, 4K-Byte x 2, 8K Byte x 2, 32K-Byte x 1, and 64K-Byte x 1) * Auto Erase (chip & sector) and Auto Program - Automatically erase any combination of sectors with Erase Suspend capability. - Automatically programs and verifies data at specified address * Erase Suspend/Erase Resume - Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation. * * * * * Status Reply - Data polling & Toggle bit for detection of program and erase cycle completion. * Chip protect/unprotect for 5V only system or 5V/12V system * 100,000 minimum erase/program cycles * Latch-up protected to 100mA from -1 to VCC+1V * Boot Code Sector Architecture - T = Top Boot Sector - B = Bottom Boot Sector * Low VCC write inhibit is equal to or less than 3.2V * Package type: - 32-pin PLCC - 32-pin TSOP - 32-pin PDIP * Boot Code Sector Architecture - T=Top Boot Sector - B=Bottom Boot Sector * 20 years data retention
GENERAL DESCRIPTION
The MX29F001T/B is a 1-mega bit Flash memory organized as 128K bytes of 8 bits only MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29F001T/B is packaged in 32-pin PLCC, TSOP, PDIP. It is designed to be reprogrammed and erased in-system or in-standard EPROM programmers. The standard MX29F001T/B offers access time as fast as 55ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29F001T/B has separate chip enable (CE) and output enable (OE) controls. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29F001T/B uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX29F001T/B uses a 5.0V 10% VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.
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PIN CONFIGURATIONS
VCC
32 PDIP
NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE NC A14 A13 A8 A9 A11 OE A10 CE Q7 Q6 Q5 Q4 Q3
32 PLCC
A12 A15 A16 NC 5 4 1
WE
32
A7 A6 A5 A4 A3 A2 A1 A0 Q0
30 29
NC
A14 A13 A8 A9
MX29F001T/B
9
MX29F001T/B
25
A11 OE A10 CE
13 14 Q1 Q2 GND
17 Q3 Q4 Q5
21 20 Q6
Q7
32 TSOP (TYPE 1)
A11 A9 A8 A13 A14 NC WE VCC NC A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE Q7 Q6 Q5 Q4 Q3 GND Q2 Q1 Q0 A0 A1 A2 A3
PIN DESCRIPTION:
SYMBOL A0~A16 Q0~Q7 CE WE OE VCC GND PIN NAME Address Input Data Input/Output Chip Enable Input Write Enable Input Output Enable Input Power Supply Pin (+5V) Ground Pin
MX29F001T/B
(NORMAL TYPE)
SECTOR STRUCTURE
A16~A0 1FFFFH 1DFFFH 1CFFFH 1BFFFH 19FFFH 17FFFH 0FFFFH 00000H 8 4 4 8 8 32 64 K-BYTE K-BYTE K-BYTE K-BYTE K-BYTE K-BYTE K-BYTE
00000H A16~A0 1FFFFH 0FFFFH 07FFFH 05FFFH 03FFFH 02FFFH 01FFFH 8 8 4 4 8 K-BYTE K-BYTE K-BYTE K-BYTE K-BYTE 64 32 K-BYTE K-BYTE
MX29F001T Sector Architecture
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MX29F001B Sector Architecture
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BLOCK DIAGRAM
WRITE CE OE WE CONTROL INPUT LOGIC HIGH VOLTAGE MACHINE (WSM) PROGRAM/ERASE STATE
X-DECODER
MX29F001T/B FLASH ARRAY ARRAY
STATE REGISTER
ADDRESS LATCH A0-A16 AND BUFFER
SENSE AMPLIFIER
Y-DECODER
Y-PASS GATE
SOURCE HV COMMAND DATA DECODER
PGM DATA HV COMMAND DATA LATCH
PROGRAM DATA LATCH
Q0-Q7
I/O BUFFER
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AUTOMATIC PROGRAMMING
The MX29F001T/B is byte programmable using the Automatic Programming algorithm. The Automatic Programming algorithm does not require the system to time out or verify the data programmed. The typical chip programming time of the MX29F001T/B at room temperature is less than 3.5 seconds.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to write commands to the command register using standard microprocessor write timings. The device will automatically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecutive read cycles provides feedback to the user as to the status of the programming operation. Register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry. During write cycles, the command register internally latches addresses and data needed for the programming and erase operations. During a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of WE . MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MX29F001T/B electrically erases all bits simultaneously using FowlerNordheim tunneling. The bytes are programmed by using the EPROM programming mechanism of hot electron injection. During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command register to respond to its full command set.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. Typical erasure at room temperature is accomplished in less than 3 second. The Automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are internally controlled within the device.
AUTOMATIC SECTOR ERASE
The MX29F001T/B is sector(s) erasable using MXIC's Auto Sector Erase algorithm. Sector erase modes allow sectors of the array to be erased in one erase cycle. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verification of electrical erase are internally con trolled by the device.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the user to only write program set-up commands (include 2 unlock write cycle and A0H) and a program command (program data and address). The device automatically times the programming pulse width, provides the program verification, and counts the number of sequences. A status bit similar to DATA polling and a status bit toggling between consecutive read cycles, provides feedback to the user as to the status of the programming operation.
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TABLE 1. SOFTWARE COMMAND DEFINITIONS
Command Bus First Bus Cycle Data F0H RD AAH AAH 2AAH 2AAH 55H 55H 555H 90H 555H 90H ADI (SA) X02H Program Chip Erase Sector Erase 4 6 6 555H 555H 555H XXXH XXXH 555H AAH AAH AAH B0H 30H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 20H 2AAH 2AAH 2AAH 55H 55H 55H 555H A0H 555H 80H 555H 80H PA 555H 555H DDI 00H 01H PD AAH AAH 2AAH 2AAH 55H 55H 555H 10H SA 30H Second Bus Cycle Addr Data Third Bus Cycle Addr Data Fourth Bus Cycle Addr Data Fifth Bus Cycle Addr Data Sixth Bus Cycle Addr Data
Cycle Addr Reset Read Read Silicon ID Chip Protect Verify 1 1 4 4 XXXH RD 555H 555H
Sector Erase Suspend 1 Sector Erase Resume Unlock for chip protect/unprotect 1 6
Note: 1. ADI = Address of Device identifier;A1=0, A0 =0 for manufacture code, A1=0, A0 =1 for device code.(Refer to Table 3) DDI = Data of Device identifier : C2H for manufacture code, 18H/19H for device code. X = X can be VIL or VIH RA=Address of memory location to be read. RD=Data to be read at location RA. 2. PA = Address of memory location to be programmed. PD = Data to be programmed at location PA. SA = Address to the sector to be erased. 3. The system should generate the following address patterns: 555H or 2AAH to Address A0~A10. Address bit A11~A16=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA). Write Sequence may be initiated with A11~A16 in either state. 4. For chip protect verify operation : If read out data is 01H, it means the chip has been protected. If read out data is 00H, it means the chip is still not being protected.
COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 1 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Either of the two reset command sequences will reset the device(when applicable).
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TABLE 2. MX29F001T/B BUS OPERATION
Pins Mode Read Silicon ID Manufacturer Code(1) Read Silicon ID Device Code(1) Read Standby Output Disable Write Chip Protect with 12V system(6) Chip Unprotect with 12V system(6) Verify Chip Protect with 12V system Chip Protect without 12V system (6) Chip Unprotect without 12V system (6) Verify Chip Protect/Unprotect without 12V system (7) Reset X X X X X X X HIGH Z L L H X H X H Code(5) L H L X X H H X L H L X X L H X L L H X H X VID(2) Code(5) L VID(2) L X X H VID(2) X L H L L L L X H H VID(2) H X H L L A0 X X A0 X A1 X X A1 X A6 X X A6 L A9 X X A9 VID(2) DOUT HIGH Z HIGH Z DIN(3) X L L H H L X VID(2) 18H/19H L L H L L X VID(2) C2H CE OE WE A0 A1 A6 A9 Q0 ~ Q7
NOTES: 1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1. 2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V. 3. Refer to Table 1 for valid Data-In during a write operation. 4. X can be VIL or VIH. 5. Code=00H means unprotected. Code=01H means protected. 6. Refer to chip protect/unprotect algorithm and waveform. Must issue "unlock for chip protect/unprotect" command before "chip protect/unprotect without 12V system" command. 7. The "verify chip protect/unprotect without 12V system" is only following "Chip protect/unprotect without 12V system" command.
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READ/RESET COMMAND
The read or reset operation is initiated by writing the read/ reset command sequence into the command register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered. If program-fail or erase-fail happen, the write of F0H will reset the device to abort the operation. A valid command must then be written to place the device in the desired state.
SET-UP AUTOMATIC CHIP ERASE COMMANDS
Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cycles are then followed by the chip erase command 10H. The Automatic Chip Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Chip Erase. Upon executing the Automatic Chip Erase, the device will automatically program and verify the entire memory for an all-zero data pattern. When the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verification begin. The erase and verification operations are completed when the data on Q7 is "1" at which time the device returns to the Read mode. The system does not require to provide any control or timing during these operations. When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array(no erase verify command is required). If the Erase operation was unsuccessful, the data on Q5 is "1"(see Table 4), indicating an erase operation exceed internal timing limit. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode.
SILICON-ID-READ COMMAND
Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not generally desired system design practice. The MX29F001T/B contains a Silicon-ID-Read operation to supplement traditional PROM programming methodology. The operation is initiated by writing the read silicon ID command sequence into the command register. Following the command write, a read cycle with A1=VIL,A0=VIL retrieves the manufacturer code of C2H. A read cycle with A1=VIL, A0=VIH returns the device code of 18H for MX29F001T,19H for MX29F001B.
TABLE 3. EXPANDED SILICON ID CODE
Pins A0 A1 VIL VIL VIL VIH VIH Q7 1 0 0 0 0 Q6 1 0 0 0 0 Q5 0 0 0 0 0 Q4 0 1 1 0 0 Q3 0 1 1 0 0 Q2 0 0 0 0 0 Q1 1 0 0 0 0 Q0 0 0 1 1 0 Code (Hex) C2H 18H 19H 01H (Protected) 00H (Unprotected)
Code Manufacture code VIL Device code VIH for MX29F001T Device code VIH for MX29F001B Chip Protection Verification X X
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SECTOR ERASE COMMANDS
The Automatic Sector Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Set-up Sector Erase command and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the device will automatically program and verify the sector(s) memory for an all-zero data pattern. The system does not require to provide any control or timing during these operations. When the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verification begin. The erase and verification operations are complete when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode. The system does not require to provide any control or timing during these operations. When using the Automatic Sector Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up command 80H. Two more "unlock" write cycles are then followed by the sector erase command 30H. The sector address is latched on the falling edge of WE, while the command(data) is latched on the rising edge of WE. Sector addresses selected are loaded into internal register on the sixth falling edge of WE. Each successive sector load cycle started by the falling edge of WE must begin within 30us from the rising edge of the preceding WE. Otherwise, the loading period ends and internal auto sector erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see section Q3, Sector Erase Timer.) Any command other than Sector Erase (30H) or Erase Suspend (B0H) during the time-out period resets the device to read mode.
ERASE SUSPEND
This command only has meaning while the state machine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out immediately terminates the timeout period and suspends the erase operation. After this command has been executed, the command register will initiate erase suspend mode. The state machine will return to read mode automatically after suspend is ready. At this time, state machine only allows the command register to respond to the Read Memory Array, Erase Resume and Program commands. The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. After an erase-suspend program operation is complete, the system can once again read array data within non-suspended sectors.
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Table 4. Write Operation Status
Status Byte Program in Auto Program Algorithm In Progress Auto Erase Algorithm Erase Suspended Mode Erase Suspend Read Erase Suspend Program (Non-Erase Suspended Sector) Byte Program in Auto Program Algorithm Exceeded Time Limits Erase in Auto Erase Algorithm Erase Suspended Mode Erase Suspend Program (Non-Erase Suspended Sector) Note: 1. Performing successive read operations from any address will cause Q6 to toggle. Q7 0 Q7 Q7 Q7 0 Data Q7 Q6 Toggle Toggle Data Toggle (Note1) Toggle Toggle Toggle 1 1 1 N/A 1 N/A Q5 0 0 Data 0 Q3 N/A 1 Data N/A
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ERASE RESUME
This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions. Another Erase Suspend command can be written after the chip has resumed erasing. WE pulse of the six write pulse sequences for chip/sector erase. The Toggle Bit feature is active during Automatic Program/Erase algorithms or sector erase time-out. (see section Q3 Sector Erase Timer)
DATA POLLING-Q7 SET-UP AUTOMATIC PROGRAM COMMANDS
To initiate Automatic Program mode, A three-cycle command sequence is required. There are two "unlock" write cycles. These are followed by writing the Automatic Program command A0H. Once the Automatic Program command is initiated, the next WE pulse causes a transition to an active programming operation. Addresses are latched on the falling edge, and data are internally latched on the rising edge of the WE pulse. The rising edge of WE also begins the programming operation. The system does not require to provide further controls or timings. The device will automatically provide an adequate internally generated program pulse and verify margin. If the program operation was unsuccessful, the data on Q5 is "1"(see Table 4), indicating the program operation exceed internal timing limit. The automatic programming operation is completed when the data read on Q6 stops toggling for two consecutive read cycles and the data on Q7 and Q6 are equivalent to data written to these two bits, at which time the device returns to the Read mode (no program verify command is required). The MX29F001T/B also features Data Polling as a method to indicate to the host system that the Automatic Program or Erase algorithms are either in progress or completed. While the Automatic Programming algorithm is in operation, an attempt to read the device will produce the complement data of the data last written to Q7. Upon completion of the Automatic Program Algorithm an attempt to read the device will produce the true data last written to Q7. The Data Polling feature is valid after the rising edge of the fourth WE pulse of the four write pulse sequences for automatic program. While the Automatic Erase algorithm is in operation, Q7 will read "0" until the erase operation is competed. Upon completion of the erase operation, the data on Q7 will read "1". The Data Polling feature is valid after the rising edge of the sixth WE pulse of six write pulse sequences for automatic chip/sector erase. The Data Polling feature is active during Automatic Program/Erase algorithm or sector erase time-out.(see section Q3 Sector Erase Timer)
WRITE OPERATION STATUS TOGGLE BIT-Q6
The MX29F001T/B features a "Toggle Bit" as a method to indicate to the host system that the Auto Program/ Erase algorithms are either in progress or complete. While the Automatic Program or Erase algorithm is in progress, successive attempts to read data from the device will result in Q6 toggling between one and zero. Once the Automatic Program or Erase algorithm is completed, Q6 will stop toggling and valid data will be read. The toggle bit is valid after the rising edge of the sixth
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Q5 Exceeded Timing Limits
Q5 will indicate if the program or erase time has exceeded the specified limits(internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle was not successfully completed. Data Polling and Toggle Bit are the only operating functions of the device under this condition. If this time-out condition occurs during sector erase operation, it is specifies that a particular sector is bad and it may not be reused. However, other sectors are still functional and may be used for the program or erase operation. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the other active sectors in the device. If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad. If this time-out condition occurs during the byte programming operation, it specifies that the entire sector containing that byte is bad and this sector may not be reused, (other sectors are still functional and can be reused). The time-out condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Automatic Algorithm operation. Hence, the system never reads a valid data on Q7 bit and Q6 never stops toggling. Once the Device has exceeded timing limits, the Q5 bit will indicate a "1". Please note that this is not a device failure condition since the device was incorrectly used.
Q3 Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If Q3 is low ("0"), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of Q3 prior to and following each subsequent sector erase command. If Q3 were high on the second status check, the command may not have been accepted.
DATA PROTECTION
The MX29F001T/B is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.
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WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns(typical) on CE or WE will not initiate a write cycle.
CHIP UNPROTECT WITH 12V SYSTEM
The MX29F001T/B also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect completion to incorporate any changes in the code. To activate this mode, the programming equipment must force VID on control pin OE and address pin A9. The CE pins must be set at VIL. Pins A6 must be set to VIH.(see Table 2) Refer to chip unprotect algorithm and waveform for the chip unprotect algorithm. The unprotection mechanism begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. It is also possible to determine if the chip is unprotected in the system by writing the Read Silicon ID command. Performing a read operation with A1=VIH, it will produce 00H at data outputs (Q0-Q7) for an unprotected sector. It is noted that all sectors are unprotected after the chip unprotect algorithm is completed.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one.
POWER SUPPLY DECOUPLING
In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected between its VCC and GND. (Using a 10uF bulk capacitor connected for high current condition is available if necessary.)
CHIP PROTECTION WITH 12V SYSTEM
The MX29F001T/B features hardware chip protection. Which will disable both program and erase operations. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest VID=12V) A6=VIL and CE=VIL.(see Table 2) Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Please refer to chip protect algorithm and waveform. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 ( with CE and OE at VIL and WE at VIH. When A1=1, it will produce a logical "1" code at device output Q0 for the protected status. Otherwise the device will produce 00H for the unprotected status. In this mode, the address, except for A1, are don't care. Address locations with A1 = VIL are reserved to read manufacturer and device codes.(Read Silicon ID) It is also possible to determine if the chip is protected in the system by writing a Read Silicon ID command. Performing a read operation with A1=VIH, it will produce a logical "1" at Q0 for the protected status.
CHIP PROTECTION WITHOUT 12V SYSTEM
The MX29F001T/B also feature a hardware chip protection method in a system without 12V power supply. The programming equipment do not need to supply 12 volts to protect all sectors. The details are shown in chip protect algorithm and waveform.
CHIP UNPROTECT WITHOUT 12V SYSTEM
The MX29F001T/B also feature a hardware chip unprotection method in a system without 12V power supply. The programming equipment do not need to supply 12 volts to unprotect all sectors. The details are shown in chip unprotect algorithm and waveform.
POWER-UP SEQUENCE
The MX29F001T/B powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences.
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ABSOLUTE MAXIMUM RATINGS
RATING Ambient Operating Temperature Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential A9 & OE VALUE 0oC to 70oC -65oC to 125oC -0.5V to 7.0V -0.5V to 7.0V -0.5V to 7.0V -0.5V to 13.5V NOTICE: Specifications contained within the following tables are subject to change. NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability.
CAPACITANCE TA = 25oC, f = 1.0 MHz
SYMBOL CIN1 CIN2 COUT PARAMETER Input Capacitance Control Pin Capacitance Output Capacitance MIN. TYP MAX. 8 12 12 UNIT pF pF pF CONDITIONS VIN = 0V VIN = 0V VOUT = 0V
READ OPERATION DC CHARACTERISTICS VCC = 5V 10% (VCC = 5V 5% for 29F001T/B-55)
SYMBOL ILI ILO ISB1 ISB2 ICC1 ICC2 VIL VIH VOL VOH1 VOH2 Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage(TTL) Output High Voltage(CMOS) 2.4 VCC-0.4 -0.3(NOTE 1) 2.0 Operating VCC current PARAMETER Input Leakage Current Output Leakage Current Standby VCC current 1 MIN. TYP MAX. 1 10 1 5 30 50 0.8 VCC + 0.3 0.45 UNIT uA uA mA uA mA mA V V V V V IOL = 2.1mA IOH = -2mA IOH = -100uA VCC=VCC MIN NOTES: 1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns. VIL min. = -2.0V for pulse width is equal to or less than 20 ns. 2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns If VIH is over the specified maximum value, read operation cannot be guaranteed. CONDITIONS VIN = GND to VCC VOUT = GND to VCC CE = VIH CE = VCC + 0.3V IOUT = 0mA, f=5MHz IOUT = 0mA, f=10MHz
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AC CHARACTERISTICS VCC = 5V 10% (5V 5% for MX29F001T/B-55)
29F001T/B-55 SYMBOL PARAMETER tACC tCE tOE tDF tOH Address to Output Delay CE to Output Delay OE to Output Delay OE High to Output Float (Note1) Address to Output hold 0 0 29F001T/B-90 SYMBOL PARAMETER tACC tCE tOE tDF tOH Address to Output Delay CE to Output Delay OE to Output Delay OE High to Output Float (Note1) Address to Output hold 0 0 MIN. MAX. 90 90 40 30 0 0 MIN. MAX. 55 55 30 20 0 0 29F001T/B-12 MIN. MAX. 120 120 50 30 UNIT ns ns ns ns ns CONDITIONS CE=OE=VIL OE=VIL CE=VIL CE=VIL CE=OE=VIL 29F001T/B-70 MIN. MAX. 70 70 40 20 UNIT ns ns ns ns ns CONDITIONS CE=OE=VIL OE=VIL CE=VIL CE=VIL CE=OE=VIL
TEST CONDITIONS:
NOTE:
* Input pulse levels: 0.45V/2.4V for 70ns max. ; 0V/3.0V for 55ns * Input rise and fall times: <10ns for 70ns max; <5ns for 55ns * Output load: 1 TTL gate + 100pF (Including scope and jig) for 70ns max. ; 1 TTL gate + 30pF (Including scope and jig) for 55ns max. * Reference levels for measuring timing : 0.8V & 2.0V for 70ns max.; 1.5V for 55ns
1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven.
P/N: PM0515
REV. 2.5,NOV. 20, 2002
14
MX29F001T/B
READ TIMING WAVEFORMS
VIH
A0~16
VIL
ADD Valid
tCE VIH
CE
VIL
WE
VIH VIL VIH VIL tACC tOH tOE tDF
OE
DATA Q0~7
VOH VOL
HIGH Z
DATA Valid
HIGH Z
COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION DC CHARACTERISTICS VCC = 5V 10% (VCC = 5V 5% for 29F001T/B-55)
SYMBOL ICC1 (Read) ICC2 ICC3 (Program) ICC4 (Erase) ICCES VCC Erase Suspend Current 2 PARAMETER Operating VCC Current MIN. TYP MAX. 30 50 50 50 UNIT mA mA mA mA mA CONDITIONS IOUT=0mA, f=5MHz IOUT=0mA, F=10MHz In Programming In Erase CE=VIH, Erase Suspended
NOTES: 1. VIL min. = -0.6V for pulse width < 20ns. 2. If VIH is over the specified maximum value, programming operation cannot be guaranteed. 3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is the sum of ICCES and ICC1 or ICC2. 4. All current are in RMS unless otherwise noted.
P/N: PM0515
REV. 2.5,NOV. 20, 2002
15
MX29F001T/B
AC CHARACTERISTICS VCC = 5V 10% (VCC = 5V 5% for 29F001T/B-55)
29F001T/B-70 SYMBOL PARAMETER tOES tCWC tCEP tCEPH1 tCEPH2 tAS tAH tDS tDH tCESC tDF tAETC tAETB tAVT tBAL tCH tCS tVLHT tOESP tWPP tWPP2 OE setup time Command programming cycle WE programming pulse width WE programming pulse width High WE programming pulse width High Address setup time Address hold time Data setup time Data hold time CE setup time before command write Output disable time (Note 1) Total erase time in auto chip erase Total erase time in auto sector erase Total programming time in auto verify Sector address load time CE Hold Time CE setup to WE going low Voltage Transition Time OE Setup Time to WE Active Write pulse width for chip protect Write pulse width for chip unprotect MIN. 0 70 45 20 20 0 45 30 0 0 30 3(TYP.) 24 1(TYP.) 8 7 100 0 0 4 4 10 12 210 29F001T/B-90 MAX. 29F001T/B-12 MIN. 0 120 50 20 20 0 50 50 0 0 40 3(TYP.) 24 1(TYP.) 8 7 100 0 0 4 4 10 12 210 3(TYP.) 1(TYP.) 7 100 0 0 4 4 10 12 40 24 8 210 MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns s s us us ns ns us us us ms
MAX. MIN. 0 90 45 20 20 0 45 45 0 0
NOTES: 1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.
P/N: PM0515
REV. 2.5,NOV. 20, 2002
16
MX29F001T/B
AC CHARACTERISTICS VCC = 5V 5% for MX29F001T/B-55
29F001T/B-55 SYMBOL PARAMETER tOES tCWC tCEP tCEPH1 tCEPH2 tAS tAH tDS tDH tCESC tDF tAETC tAETB tAVT tBAL tCH tCS tVLHT tOESP tWPP tWPP2 OE setup time Command programming cycle WE programming pulse width WE programming pulse width High WE programming pulse width High Address setup time Address hold time Data setup time Data hold time CE setup time before command write Output disable time (Note 1) Total erase time in auto chip erase Total erase time in auto sector erase Total programming time in auto verify Sector address load time CE Hold Time CE setup to WE going low Voltage Transition Time OE Setup Time to WE Active Write pulse width for chip protect Write pulse width for chip unprotect 3(TYP.) 1(TYP.) 7 100 0 0 4 4 10 12 MIN. 0 70 45 20 20 0 45 20 0 0 20 24 8 210 MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns s s us us ns ns us us us ms
NOTES: 1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.
P/N: PM0515
REV. 2.5,NOV. 20, 2002
17
MX29F001T/B
SWITCHING TEST CIRCUITS
DEVICE UNDER TEST
1.6K ohm +5V
CL
1.2K ohm
DIODES=IN3064 OR EQUIVALENT
CL=100pF Including jig capacitance for 29F001T/B-70, 29F001T/B-90, 29F001T/B-12 30pF Including jig capacitance for 29F001T/B-55
SWITCHING TEST WAVEFORMS(I) for 29F001T/B-70, 29F001T/B-90, 29F001T/B-12
2.4 V 2.0V TEST POINTS 0.8V 0.45 V INPUT 0.8V OUTPUT 2.0V
AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". Input pulse rise and fall times are < 10ns.
SWITCHING TEST WAVEFORMS(II) for 29F001T/B-55
3.0 V 1.5V 0V INPUT OUTPUT
AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0". Input pulse rise and fall times are < 5ns.
TEST POINTS
1.5V
P/N: PM0515
REV. 2.5,NOV. 20, 2002
18
MX29F001T/B
COMMAND WRITE TIMING WAVEFORM
VCC
5V
ADD A0~16
VIH
ADD Valid
VIL tAS tAH
WE
VIH VIL tOES tCEPH1 tCWC
tCEP
CE
VIH VIL tCS tCH
OE
VIH VIL VIH tDS tDH
DATA Q0-7
DIN
VIL
P/N: PM0515
REV. 2.5,NOV. 20, 2002
19
MX29F001T/B
AUTOMATIC PROGRAMMING TIMING WAVEFORM
One byte data is programmed. Verification in fast algorithm and additional programming by external control are not required because these operations are executed automatically by internal control circuit. Programming completion can be verified by DATA polling and toggle bit checking after automatic verify starts. Device outputs DATA during programming and DATA after programming on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform)
AUTOMATIC PROGRAMMING TIMING WAVEFORM
Vcc 5V
A11~A16
ADD Valid
A0~A10 WE
555H
2AAH
555H
ADD Valid
tAS tAH
tCWC tCEPH1 tAVT tCESC
CE tCEP OE tDS tDH Q0~Q2 ,Q4(Note 1) Q7
Command In Command #AAH Command In Command #55H Command In Command #A0H Data In Command In Command In Command In Data In DATA
tDF
DATA polling
DATA DATA
(Q0~Q7) Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit
tOE
P/N: PM0515
REV. 2.5,NOV. 20, 2002
20
MX29F001T/B
AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data A0H Address 555H
Write Program Data/Address
Toggle Bit Checking Q6 not Toggled YES
NO
Invalid Command
NO Verify Byte Ok
YES NO Auto Program Completed Q5 = 1 YES
.
Reset
Auto Program Exceed Timing Limit
P/N: PM0515
REV. 2.5,NOV. 20, 2002
21
MX29F001T/B
TOGGLE BIT ALGORITHM
START
Read Q7~Q0
Read Q7~Q0
(Note 1)
Toggle Bit Q6 =Toggle? YES
NO
NO Q5=1?
YES Read Q7~Q0 Twice (Note 1,2)
Toggle Bit Q6= Toggle? YES Program/Erase Operation Not Complete, Write Reset Command
NO
Program/Erase Operation Complete
Notes: 1.Read toggle bit Q6 twice to determine whether or not it is toggle. See text. 2.Recheck toggle bit Q6 because it may stop toggling as Q5 changes to "1". See text.
P/N: PM0515
REV. 2.5,NOV. 20, 2002
22
MX29F001T/B
AUTOMATIC CHIP ERASE TIMING WAVEFORM
All data in chip are erased. External erase verification is not required because data is erased automatically by internal control circuit. Erasure completion can be verified by DATA polling and toggle bit checking after auto matic erase starts. Device outputs 0 during erasure and 1 after erasure 0n Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform)
AUTOMATIC CHIP ERASE TIMING WAVEFORM
Vcc 5V
A11~A16
A0~A10 WE
555H
2AAH
555H
555H
2AAH
555H
tAS tAH
tCWC tCEPH1
tAETC
CE tCEP OE tDS tDH Q0,Q1, Q4(Note 1) Q7
Command In Command #AAH Command In Command #55H Command In Command #80H Command In Command #AAH Command In Command #55H Command In Command #10H Command In Command In Command In Command In Command In Command In
DATA polling
(Q0~Q7) Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit
P/N: PM0515
REV. 2.5,NOV. 20, 2002
23
MX29F001T/B
AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 10H Address 555H
Toggle Bit Checking Q6 not Toggled YES
NO
Invalid Command
NO
DATA Polling Q7 = 1 YES NO . Q5 = 1
Auto Chip Erase Completed
YES Reset
Auto Chip Erase Exceed Timing Limit
P/N: PM0515
REV. 2.5,NOV. 20, 2002
24
MX29F001T/B
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Sector data indicated by A13 to A16 are erased. External erase verify is not required because data are erased automatically by internal control circuit. Erasure completion can be verified by DATA polling and toggle bit checking after automatic erase starts. Device outputs 0 during erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform)
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Vcc 5V
A13~A16
Sector Address0
Sector Address1
Sector Addressn
A0~A10
555H tAS tAH
2AAH
555H
555H
2AAH tCWC
WE
tCEPH1 tBAL tAETB
CE
tCEP
OE
tDS tDH
Q0,Q1, Q4(Note 1)
Command In
Command In
Command In
Command In
Command In
Command In
Command In
Command In
DATA polling
Q7
Command In
Command In
Command In
Command In
Command In
Command In
Command In Command #30H
Command In Command #30H
Command #AAH Command #55H Command #80H Command #AAH Command #55H Command #30H (Q0~Q7)
Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit
P/N: PM0515
REV. 2.5,NOV. 20, 2002
25
MX29F001T/B
AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 30H Sector Address
Toggle Bit Checking Q6 Toggled ?
NO Invalid Command
YES Load Other Sector Addrss If Necessary (Load Other Sector Address)
Last Sector to Erase YES
NO
Time-out Bit Checking Q3=1 ?
NO
YES NO
Toggle Bit Checking Q6 not Toggled YES
NO DATA Polling Q7 = 1 Q5 = 1
.
YES Reset Auto Sector Erase Completed
Auto Sector Erase Exceed Timing
P/N: PM0515
REV. 2.5,NOV. 20, 2002
26
MX29F001T/B
ERASE SUSPEND/ERASE RESUME FLOWCHART
START
Write Data B0H
NO Toggle Bit checking Q6 not toggled YES Read Array or Program
Reading or Programming End YES Write Data 30H
NO
Continue Erase
Another Erase Suspend ? YES
NO
.
P/N: PM0515
REV. 2.5,NOV. 20, 2002
27
MX29F001T/B
TIMING WAVEFORM FOR CHIP PROTECTION FOR SYSTEM WITH 12V
A1
A6
12V 5V A9
tVLHT Verify
12V 5V OE
tVLHT tWPP 1 tVLHT
WE
tOESP
CE
Data
tOE
01H
F0H
P/N: PM0515
REV. 2.5,NOV. 20, 2002
28
MX29F001T/B
TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V
A1
12V 5V A9
tVLHT
A6
Verify
12V 5V OE
tVLHT tWPP 2 tVLHT
WE
tOESP
CE
Data
tOE
00H
F0H
P/N: PM0515
REV. 2.5,NOV. 20, 2002
29
MX29F001T/B
CHIP PROTECTION ALGORITHM FOR SYSTEM WITH 12V
START
PLSCNT=1
OE=VID,A9=VID,CE=VIL A6=VIL
Activate WE Pulse
Time Out 10us
Device Failed Set WE=VIH, CE=OE=VIL A9 should remain VID
No
Read from Sector Addr=SA, A1=1
PLSCNT=32?
No
Data=01H?
Yes Device Failed Remove VID from A9 Write Reset Command
Chip Protection Complete
P/N: PM0515
REV. 2.5,NOV. 20, 2002
30
MX29F001T/B
CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITH 12V
START
PLSCNT=1
Set OE=A9=VID CE=VIL,A6=1
Activate WE Pulse
Time Out 12ms
Increment PLSCNT
Set OE=CE=VIL A9=VID,A1=1
Read Data from Device No
Data=00H?
No PLSCNT=1000?
Yes Remove VID from A9 Write Reset Command
Yes Device Failed
Chip Unprotect Complete
P/N: PM0515
REV. 2.5,NOV. 20, 2002
31
MX29F001T/B
TIMING WAVEFORM FOR CHIP PROTECTION FOR SYSTEM WITHOUT 12V
A1
A6
Toggle bit polling
Verify
5V OE
tCEP
WE
* See the following Note!
CE
Data
Don't care (Note 2) tOE
01H
F0H
Note: 1. Must issue "unlock for sector protect/unprotect" command before chip protection for a system without 12V provided. 2. Except F0H
P/N: PM0515
REV. 2.5,NOV. 20, 2002
32
MX29F001T/B
TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12V
A1
A6
Toggle bit polling
Verify
5V OE
tCEP
WE
* See the following Note!
CE
Data
Don't care (Note 2) tOE
00H
F0H
Note: 1. Must issue "unlock for sector protect/unprotect" command before chip unprotection for a system without 12V provided. 2. Except F0H
P/N: PM0515
REV. 2.5,NOV. 20, 2002
33
MX29F001T/B
CHIP PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V
START
PLSCNT=1
Write "unlock for chip protect/unprotect" Command(Table1)
OE=VIH,A9=VIH CE=VIL,A6=VIL
Activate WE Pulse to start Data don't care
Toggle bit checking DQ6 not Toggled Yes Increment PLSCNT Set CE=OE=VIL A9=VIH
No
.
No
Raed from Sector Addr=SA, A1=1
PLSCNT=32?
No
Data=01H?
Yes Device Failed
Yes Write Reset Command
Chip Protection Complete
P/N: PM0515
REV. 2.5,NOV. 20, 2002
34
MX29F001T/B
CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V
START
PLSCNT=1
Write "unlock for chip protect/unprotect" Command (Table 1)
Set OE=A9=VIH CE=VIL,A6=1
Activate WE Pulse to start Data don't care
No
Toggle bit checking DQ6 not Toggled Yes Set OE=CE=VIL A9=VIH,A1=1
Increment PLSCNT
Read Data from Device No
Data=00H?
No
PLSCNT=1000?
Yes Write Reset Command
Yes Device Failed
Chip Unprotect Complete
P/N: PM0515
REV. 2.5,NOV. 20, 2002
35
MX29F001T/B
ID CODE READ TIMING WAVEFORM
VCC
5V VID VIH VIL
ADD A9
tACC
tACC
A1
VIH VIL
ADD A2-A8 A10-A16 CE
VIH VIL
VIH VIL
WE
VIH VIL
tCE
OE
VIH VIL
tOE tDF tOH tOH
VIH
DATA Q0-Q7
DATA OUT
VIL
DATA OUT 18H/19H
C2H
P/N: PM0515
REV. 2.5,NOV. 20, 2002
36
MX29F001T/B
ERASE AND PROGRAMMING PERFORMANCE (1)
LIMITS PARAMETER Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time Erase/Program Cycles Note: 100,000 MIN. TYP.(2) 1 3 7 3.5 MAX.(3) 8 24 210 10.5 UNITS s s us sec Cycles
1.Not 100% Tested, Excludes external system level over head. 2.Typical values measured at 25C, 5V. 3.Maximum values measured at 25 4.5V. C,
LATCH-UP CHARACTERISTICS
MIN. Input Voltage with respect to GND on all pins except I/O pins Input Voltage with respect to GND on all I/O pins Current Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time. -1.0V -1.0V -100mA MAX. 13.5V Vcc + 1.0V +100mA
DATA RETENTION
PARAMETER Data Retention Time MIN. 20 UNIT Years
P/N: PM0515
REV. 2.5,NOV. 20, 2002
37
MX29F001T/B
ORDERING INFORMATION
PLASTIC PACKAGE (Top Boot Sector as an sample For Bottom Boot Sector ones,MX29F001Txx will change to MX29F001Bxx) PART NO. MX29F001TQC-55 MX29F001TQC-70 MX29F001TQC-90 MX29F001TQC-12 MX29F001TTC-55 MX29F001TTC-70 MX29F001TTC-90 MX29F001TTC-12 MX29F001TPC-55 MX29F001TPC-70 MX29F001TPC-90 MX29F001TPC-12 ACCESS TIME (ns) 55 70 90 120 55 70 90 120 55 70 90 120 OPERATING CURRENT MAX.(mA) 30 30 30 30 30 30 30 30 30 30 30 30 STANDBY CURRENT MAX.(uA) 5 5 5 5 5 5 5 5 5 5 5 5 32 Pin PLCC 32 Pin PLCC 32 Pin PLCC 32 Pin PLCC 32 Pin TSOP (Normal Type) 32 Pin TSOP (Normal Type) 32 Pin TSOP (Normal Type) 32 Pin TSOP (Normal Type) 32 Pin PDIP 32 Pin PDIP 32 Pin PDIP 32 Pin PDIP PACKAGE
P/N: PM0515
REV. 2.5,NOV. 20, 2002
38
MX29F001T/B
PACKAGE INFORMATION
P/N: PM0515
REV. 2.5,NOV. 20, 2002
39
MX29F001T/B
P/N: PM0515
REV. 2.5,NOV. 20, 2002
40
MX29F001T/B
P/N: PM0515
REV. 2.5,NOV. 20, 2002
41
MX29F001T/B
REVISION HISTORY
Revision 2.0 Description 1. To remove "Advanced Information" data sheet marking and contain information on products in full production 2.The modification summary from Revision 0.0 to Revision 1.0: 2-1.Program/erase cycle times:10K cycles-->100K cycles 2-2.To add data retention 20 years 2-3.To remove A9 from the timing waveform of protection/ unprotection without 12V 2-4.Multi-sector erase time out:80ms-->30us 2-5.tBAL:80us-->100us To modify "Package Information" To corrected typing error 1. Add industrial grade spec 2. Modify maximum value measurement temperature from 25 to 85 C C 1. Remove industrial grade spec 1. To modify Package Information Page P1 Date DEC/21/1999
P1,38 P1,38 P32,33 P8 P16,17 P39~41 All P13,38 P37 P13,37,38 P39~41
2.1 2.2 2.3 2.4 2.5
JUN/14/2001 JUL/01/2002 JUL/09/2002 AUG/12/2002 NOV/20/2002
P/N: PM0515
REV. 2.5,NOV. 20, 2002
42
MX29F001T/B
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688 FAX:+886-3-563-2888
EUROPE OFFICE:
TEL:+32-2-456-8020 FAX:+32-2-456-8021
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TEL:+81-44-246-9100 FAX:+81-44-246-9105
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TEL:+65-348-8385 FAX:+65-348-8096
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TEL:+886-2-2509-3300 FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088 FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900 FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

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